Semiconductor device and method of manufacturing the same

ABSTRACT

A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.13/952,869, filed Jul. 29, 2013, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2012-198568filed on Sep. 10, 2012, the disclosures of which are incorporated hereinby reference in their entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method ofmanufacturing the same, and to a semiconductor device having a verticaltransistor structure and a method of manufacturing the semiconductordevice.

In recent years, a high-capacity and small-sized Li-ion (lithium-ion)battery has been used in various products including cell phones andnotebook PCs. Although the Li-ion battery has high performance, heatgeneration and deterioration due to overcharge, overdischarge, shortcircuit or the like are likely to occur therein, and a problem such asburst arises depending on a case. A protection circuit is needed inorder to safely use the Li-ion battery. Therefore, in a battery pack,there is provided a protection circuit substrate that monitorsovercharge, overdischarge, overcurrent, abnormal heat generation and thelike, and controls charge and discharge.

The protection circuit substrate is provided with a MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor), a resistor, atemperature detection element and a control IC. The MOSFET switchesON/OFF a charge path and a discharge path. As the MOSFET, there is used,for example, a bidirectional MOSFET in which two FETs having a commondrain electrode are formed into one chip. The resistor detects a chargeand discharge current. The temperature detection element detectstemperatures of the MOSFET and the protection circuit substrate, and,for example, a thermistor or the like is used as a temperature detectionelement. The control IC processes information from these elements, andcontrols the MOSFET.

With the progress of size reduction and price reduction of cell phonesand notebook PCs, size reduction, thickness reduction, and pricereduction are required also for the protection circuit substrate. Insuch a situation, a technology of mounting a temperature detectionelement on a MOSFET is been proposed. In Japanese Patent Laid-Open No.2004-31980 (Patent Document 1), a temperature detection element isprovided at a position adjacent to a source pad over an active regionhaving a highest temperature over a region where a power MOSFET isformed. This temperature detection element is coupled to a controlcircuit formation region in a same chip, and a detection signal cannotbe extracted outside.

Japanese Patent Laid-Open No. 2007-95848 (Patent Document 2) describes atechnology in which two bipolar transistors coupled to gates of twooutput MOSFETs, respectively are provided, and in which overheatedstates of the output MOSFETs are detected by detecting leakage currentsof the respective bipolar transistors.

SUMMARY

In Patent Document 2, since the bipolar transistors are coupled to thegates of the output MOSFETs, a capacity coupled to the gates increases.Because of this, there is a possibility that the output MOSFETs areaffected by the bipolar transistors, and that operating speeds thereofbecome slow.

The other problems and the new feature will become clear from thedescription of the present specification and the accompanying drawings.

According to one embodiment, in a semiconductor device, there isarranged a temperature detection diode between a first source terminalof the first MOSFET formed in a first region and a second sourceterminal of the second MOSFET formed in a second region of a chip. Adirection in which a first terminal and a second terminal of thetemperature detection diode are aligned is a first directionsubstantially parallel to a direction in which the first source terminaland a first gate terminal of the first MOSFET are aligned, or a seconddirection substantially perpendicular thereto.

According to the present embodiment, it becomes possible to performtemperature detection without affecting operation of the MOSFETs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a semiconductordevice according to a First Embodiment;

FIG. 2 is a diagram showing a surface layout of the semiconductor deviceshown in FIG. 1;

FIG. 3 is a cross-sectional diagram of the semiconductor device takenalong a line III-III shown in FIG. 2;

FIG. 4 is a cross-sectional diagram of the semiconductor device takenalong a line IV-IV shown in FIG. 2;

FIG. 5 is a diagram showing a configuration of a temperature detectiondiode used for the semiconductor device shown in FIG. 2;

FIG. 6 is a partially enlarged cross-sectional diagram of thetemperature detection diode shown in FIG. 5;

FIG. 7 is a diagram showing a configuration of a bidirectional Zenerdiode used for the semiconductor device shown in FIG. 2;

FIG. 8A is a manufacturing process cross-sectional diagram explaining amethod of manufacturing the semiconductor device according to the FirstEmbodiment;

FIG. 8B is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 8C is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 8D is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 8E is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 8F is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 8G is a manufacturing process cross-sectional diagram explainingthe method of manufacturing the semiconductor device according to theFirst Embodiment;

FIG. 9 is a circuit diagram showing a configuration of a batteryprotection circuit using the semiconductor device according to the FirstEmbodiment;

FIG. 10 is a diagram showing a state where the battery protectioncircuit using the semiconductor device according to the First Embodimentis mounted on a substrate;

FIG. 11 is a diagram showing the state where the battery protectioncircuit using the semiconductor device according to the First Embodimentis mounted on the substrate;

FIG. 12 is a partially enlarged cross-sectional diagram of a temperaturedetection diode used for a semiconductor device according to a SecondEmbodiment;

FIG. 13A is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13B is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13C is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13D is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13E is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13F is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13G is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13H is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 13 is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Second Embodiment;

FIG. 14 is a partially enlarged cross-sectional diagram of a temperaturedetection diode used for a semiconductor device according to a ThirdEmbodiment;

FIG. 15A is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15B is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15C is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15D is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15E is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15F is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15G is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15H is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 15I is a manufacturing process cross-sectional diagram of thesemiconductor device according to the Third Embodiment;

FIG. 16 is a circuit diagram showing a configuration of a semiconductordevice according to a Fourth Embodiment;

FIG. 17 is a diagram showing a surface layout of the semiconductordevice shown in FIG. 16;

FIG. 18 is a cross-sectional diagram of the semiconductor device takenalong a line XVIII-XVIII shown in FIG. 17;

FIG. 19 is a cross-sectional diagram of the semiconductor device takenalong a line XIX-XIX shown in FIG. 17;

FIG. 20 is a diagram showing a configuration of a protection diode usedfor the semiconductor device shown in FIG. 17;

FIG. 21 is a circuit diagram showing a configuration of a semiconductordevice according to a Fifth Embodiment;

FIG. 22 is a diagram showing a surface layout of the semiconductordevice shown in FIG. 21;

FIG. 23 is a cross-sectional diagram of the semiconductor device takenalong a line XXIII-XXIII shown in FIG. 22;

FIG. 24 is a cross-sectional diagram of the semiconductor device takenalong a line XXIV-XXIV shown in FIG. 22;

FIG. 25 is a cross-sectional diagram of the semiconductor device takenalong a line XXV-XXV shown in FIG. 22;

FIG. 26 is a diagram showing a surface layout of a semiconductor deviceaccording to a Sixth Embodiment;

FIG. 27 is a cross-sectional diagram of the semiconductor device takenalong a line XXVII-XXVII shown in FIG. 26;

FIG. 28 is a cross-sectional diagram of the semiconductor device takenalong a line XXVIII-XXVIII shown in FIG. 26;

FIG. 29 is a cross-sectional diagram of the semiconductor device takenalong a line XXIX-XXIX shown in FIG. 26;

FIG. 30 is a diagram showing a surface layout of a semiconductor deviceaccording to a Seventh Embodiment; and

FIG. 31 is a diagram showing a surface layout of a semiconductor deviceaccording to an Eighth Embodiment.

DETAILED DESCRIPTION

The present embodiment relates to a semiconductor device and a method ofmanufacturing the semiconductor device, and relates to, for example, asemiconductor device that has a charge and discharge control MOSFET of aLi-ion battery in which two MOFETs having a common drain electrode areformed into one chip or that has a similar vertical transistorstructure, and a method of manufacturing the same.

The semiconductor device according to the present embodiment is, forexample, a CSP (Chip size package) type MOSFET having a pad providedover a chip, and is flip-chip mounted. A temperature detection diode isincorporated in the MOSFET, and cost reduction, size reduction, andthickness reduction of a protection circuit substrate on which theMOSFET is mounted can be achieved.

In addition, in consideration of terminal arrangement, elementarrangement, and an element structure of the temperature detection diodein the semiconductor device, a most suitable layout is provided in orderto solve a problem of an increasing chip size. Because of this, itbecomes possible to accurately detect heat generation of the MOSFETsimultaneously with the cost reduction, size reduction, and thicknessreduction of the protection circuit substrate, and thus a small andsafer battery pack can be achieved. Hereinafter, a specificconfiguration of the present embodiment will be explained.

First Embodiment

A semiconductor device according to a First Embodiment will be explainedwith reference to drawings. In the following drawings, the same symbolis attached to the same component, and explanation thereof isappropriately omitted. FIG. 1 is a circuit diagram showing aconfiguration of a semiconductor device 1 according to the FirstEmbodiment. As shown in FIG. 1, the semiconductor device 1 is providedwith two N-channel-type MOSFETs (hereinafter referred to as a MOS1 and aMOS2), Zener diodes 2 and 3, and a temperature detection diode 4.

A drain is coupled in common to the MOS1 and the MOS2. A source of theMOS1 is coupled to a source terminal S1, and a gate thereof is coupledto a gate terminal G1. A source of the MOS2 is coupled to a sourceterminal S2, and a gate thereof is coupled to a gate terminal G2. Notethat the MOS1 and the MOS2 may be P-channel-type MOSFETs.

In the First Embodiment, the temperature detection diode 4 has aconfiguration in which a plurality of diode elements has been coupled inseries. Although the temperature detection diode 4 includes four-stagediode element in an example shown in FIG. 1, the appropriate number ofstages can be selected depending on an external application. An anode ofthe temperature detection diode 4 is coupled to an anode terminal T1 (afirst terminal), and a cathode thereof is coupled to a cathode terminalT2 (a second terminal). The temperature detection diode 4 is not coupledto any of the MOS1 and the MOS2 in the semiconductor device 1.Therefore, it becomes possible to perform temperature detection withoutaffecting operation of the MOSFETs in the First Embodiment.

The bidirectional Zener diodes 2 and 3 for gate protection are providedbetween the gates and the sources of the MOS1 and the MOS2,respectively. Note that, although the bidirectional Zener diodes 2 and 3respectively include one-stage diode element in the example shown inFIG. 1, plural stages of diode elements may be coupled in some cases inaccordance with a withstand voltage of a MOSFET to be protected. Notethat a bidirectional Zener diode may not be provided.

A layout of a chip surface of the semiconductor device 1 according tothe First Embodiment is shown in FIG. 2. As shown in FIG. 2, the chip isdivided into a first region 10 and a second region 20. In FIG. 2, aboundary line of the first region 10 and the second region 20 is shownby a dashed line. The MOS1 is formed in the first region 10, and theMOS2 is formed in the second region 20. The source terminal S1 and thegate terminal G1 which have been coupled to the MOS1 are arranged in thefirst region 10. The source terminal S2 and the gate terminal G2 whichhave been coupled to the MOS2 are arranged in the second region 20. Adirection in which the source terminal S1 and the gate terminal G1 arealigned, and a direction in which the source terminal S2 and the gateterminal G2 are aligned are substantially parallel to each other. Here,the direction in which the source terminal S1 and the gate terminal G1are aligned, and the direction in which the source terminal S2 and thegate terminal G2 are aligned are defined as a Y direction (a firstdirection).

The source terminal S1 and the source terminal S2 are arranged facingeach other while sandwiching the boundary of the first region 10 and thesecond region 20. The gate terminal G1 and the gate terminal G2 arearranged facing each other while sandwiching the boundary of the firstregion 10 and the second region 20. A direction in which the sourceterminal S1 and the source terminal S2 are aligned, and a direction inwhich the gate terminal G1 and the gate terminal G2 are aligned aresubstantially parallel to each other. Here, the direction in which thesource terminal S1 and the source terminal S2 are aligned, and thedirection in which the gate terminal G1 and the gate terminal G2 arealigned are defined as an X direction (a second direction). Thetemperature detection diode 4 is arranged between the source terminal S1and the source terminal S2. The temperature detection diode 4 isarranged between the first region 10 where the MOS1 is formed, and thesecond region 20 where the MOS2 is formed.

The anode terminal T1 and the cathode terminal T2 of the temperaturedetection diode 4 are arranged between the first region 10 and thesecond region 20. The anode terminal T1 and the cathode terminal T2 arearranged so as to be aligned in the Y direction (the first direction).

The anode terminal T1 is arranged between the source terminal S1 and thesource terminal S2. That is, the source terminal S1, the anode terminalT1, and the source terminal S2 are arranged so as to be aligned in thisorder in the X direction (second direction).

The anode terminal T1 is arranged at an intersection of a straight linethat passes through the source terminal S1 and the source terminal S2,and the boundary line of the first region 10 and the second region 20. Adistance between the source terminal S1 and the anode terminal T1, and adistance between the source terminal S2 and the anode terminal T1 aresubstantially equal to each other. The temperature detection diode 4 islaid out in a lower portion of the anode terminal T1, with theintersection of the straight line that passes through the sourceterminal S1 and the source terminal S2, and the boundary line of thefirst region 10 and the second region 20 being as a center.

The cathode terminal T2 is arranged between the gate terminal G1 and thegate terminal G2. That is, the gate terminal G1, the cathode terminalT2, and the gate terminal G2 are arranged so as to be aligned in thisorder in the X direction (the second direction). A distance between thegate terminal G1 and the cathode terminal T2, and a distance between thegate terminal G2 and the cathode terminal T2 are substantially equal toeach other.

A distance between the source terminal S1 and the gate terminal G1, adistance between the anode terminal T1 and the cathode terminal T2, anda distance between the source terminal S2 and the gate terminal G2 aresubstantially equal to one another. The source terminals S1 and S2, thegate terminals G1 and G2, the anode terminal T1, and the cathodeterminal T2 are respectively fixed to a protection circuit substrate bysolder or the like, and are connected. Deviation of a connectingposition of the semiconductor device when melting of solder by heatcauses connection can be suppressed by equalizing a pitch of theterminals.

A source aluminum wiring 11 of the MOS1 is laid out over a surface ofthe first region 10, and a source aluminum wiring 21 of the MOS2 is laidout over a surface of the second region 20. A plurality of cells of theMOSFET is arranged under these wirings. A gate aluminum wiring 12 isarranged at an outer periphery of the source aluminum wiring 11 so as tosurround the source aluminum wiring 11. The gate aluminum wiring 12 iscoupled to the gate terminal G1 by a leader line 13.

A gate aluminum wiring 22 is arranged at an outer periphery of thesource aluminum wiring 21 so as to surround the source aluminum wiring21. The gate aluminum wiring 22 is coupled to the gate terminal G2 by aleader line 23. A separation wiring 30 is arranged at outer peripheriesof the gate aluminum wiring 12 and the gate aluminum wiring 22. Theseparation wiring 30 is a ring-shaped wiring also referred to as an EQR(EQui-potential Ring). By keeping the separation wiring 30 at a drainpotential, the spread of a depletion layer is suppressed so that thedepletion layer does not reach an edge of the chip, and a withstandvoltage of the chip edge can be maintained.

An anode wiring 41 is formed at the lower portion of the anode terminalT1, and a cathode wiring 42 is formed at a lower portion of the cathodeterminal T2. The cathode wiring 42 is drawn so as to surround theperiphery of the anode wiring 41. A drain electrode that is not shown inFIG. 2 is provided on aback surface of the semiconductor device 1. Thisdrain electrode is shared by the MOS1 and the MOS2.

Here, a cross-sectional structure of the semiconductor device 1 will beexplained with reference to FIGS. 3 and 4. FIG. 3 is a cross-sectionalview taken along a line of FIG. 2, and FIG. 4 is a cross-sectional viewtaken along a line IV-IV of FIG. 2. As shown in FIG. 3, thesemiconductor device 1 further has a semiconductor substrate 5, a baseregion 6, a gate trench 7, a drain electrode 8, an interlayer insulatingfilm 31, a contact 32, a protective insulating film 33 and the like.

The semiconductor substrate 5 is, for example, an N-type semiconductorsubstrate including Si. An N-type epitaxial region that is not shown isformed at the semiconductor substrate 5. The semiconductor substrate 5and the epitaxial region work as a drain region. The P-type base region6 and the gate trench 7 are formed at the semiconductor substrate 5. Thebase region 6 works as a channel region. The gate trench 7 and a sourceregion, although not shown, are formed in the base region 6. A gateelectrode, which includes polysilicon and the like, and a gateinsulating film which are not shown, are formed in the gate trench 7.Furthermore, an interlayer insulating film and the like may be formed inthe gate trench 7. On the whole, a vertical transistor structure isformed under both regions where the source aluminum wiring 11 and thesource aluminum wiring 21 have been formed.

Between the MOS1 and the MOS2, the temperature detection diode 4 isprovided over the semiconductor substrate 5 via an insulating film 40.Here, a structure of the temperature detection diode 4 will be explainedwith reference to FIGS. 5 and 6. FIG. 5 is a diagram when thetemperature detection diode 4 is viewed from a top surface, and FIG. 6is a partially enlarged cross-sectional diagram of FIG. 5.

As shown in FIG. 5, the temperature detection diode 4 has aconfiguration in which a connection structure including P-typepolysilicon 43 and N-type polysilicon 44 and constituting a plurality ofPN junctions has been concentrically arranged. As shown in FIG. 6, acontact metal is provided between adjacent connection structures,respectively. The formation of the contact metal 47 in an NP junctionportion between the PN junctions eliminates the NP junctions, and thus abidirectional diode is converted into a multistage diode row.

A plurality of anode contacts 45 is provided on the P-type polysilicon43 provided in a center. As shown in FIG. 3, the anode wiring 41 and theanode terminal T1 are provided at an upper layer of the anode contact45. The anode terminal T1 and the P-type polysilicon 43 are coupled toeach other via the anode contact 45 and the anode wiring 41.

A plurality of cathode contacts 46 is provided on the N-type polysilicon44 provided at an outermost periphery. As shown in FIGS. 3 and 4, thecathode wiring 42 is provided on an upper layer of the cathode contact46, and the cathode terminal T2 is provided on an upper layer of thecathode wiring 42. The cathode terminal T2 and the N-type polysilicon 44are coupled to each other via the cathode contact 46 and the cathodewiring 42. That is, the temperature detection diode 4 is concentricallyconfigured, with the anode terminal T1 that is the first terminal beingas a center.

Referring to FIG. 3, the interlayer insulating film 31 is provided, overthe semiconductor substrate 5 and the temperature detection diode 4, soas to cover them. Over the interlayer insulating film 31, there isprovided a wiring layer including the above-mentioned source aluminumwiring 11, the gate aluminum wiring 12, the source aluminum wiring 21,the gate aluminum wiring 22, the separation wiring 30, the anode wiring41, and the cathode wiring 42. The source aluminum wiring 11, the gatealuminum wiring 12, the source aluminum wiring 21, the gate aluminumwiring 22, and the separation wiring 30 are coupled to the base region6, the gate trench 7, and the like in a lower layer, respectively, viathe contact 32 provided in the interlayer insulating film 31.

Referring to FIG. 4, the bidirectional Zener diodes 2 and 3 are formedat lower portions of the gate terminals G1 and G2, respectively. Here,configurations of the bidirectional Zener diodes 2 and 3 will beexplained with reference to FIG. 7. FIG. 7 is a diagram showing theconfigurations of the bidirectional Zener diodes 2 and 3. Note thatsince the configurations of the bidirectional Zener diodes 2 and 3 arethe same as each other, only the configuration of the bidirectionalZener diode 2 will be explained here.

The bidirectional Zener diode 2 is formed over the semiconductorsubstrate 5 via the insulating film 40. Referring to FIG. 7, thebidirectional Zener diode 2 has the configuration in which a P-typepolysilicon 25 and an N-type polysilicon 26 have been alternately andconcentrically formed. A plurality of contacts 27 is provided at theP-type polysilicon 25 provided in a center. The P-type polysilicon 25provided in the center is coupled to the gate aluminum wiring 12 via thecontacts 27. A plurality of contacts 28 is provided on the P-typepolysilicon 25 provided at an outermost periphery. The P-typepolysilicon 25 provided at the outermost periphery is coupled to thesource aluminum wiring 11 via the contacts 28.

The protective insulating film 33 is provided over the wiring layer soas to cover it. The source terminal S1 is formed over the sourcealuminum wiring 11, and the source terminal S2 is formed over the sourcealuminum wiring 21. In addition, the anode terminal T1 is formed overthe anode wiring 41, and the cathode terminal T2 is formed over thecathode wiring 42. The gate terminal G1 is formed over the leader line13, and the gate terminal G2 is formed over the leader line 23. Thesource terminals S1 and S2, the gate terminals G1 and G2, the anodeterminal T1, and the cathode terminal T2 are exposed from the protectiveinsulating film 33.

A drain electrode 8 is provided on a back surface side of thesemiconductor substrate 5. In the semiconductor device having thepresent configuration, when a current flows from the source terminal S1toward the source terminal S2, a current path is formed in a directionof the source terminal S2 via the drain electrode 8 of the back surfacefrom the source terminal S1 as shown by an arrow of FIG. 3. Note thatthe vertical transistor structure may have any configuration, as long asit is the structure of flowing a current in a direction via the sourcealuminum wiring 11 of the surface of the chip, the drain electrode 8 ofthe back surface, and the source aluminum wiring 21 of the surface ofthe chip so that the current flows vertically in the semiconductorsubstrate 5. In addition, the above-described configuration is oneexample, and the N-type and the P-type may be opposite to each other.

As mentioned above, the anode terminal T1 is arranged at theintersection of the straight line that passes through the sourceterminal S1 and the source terminal S2, and the boundary line of theMOS1 and the MOS2, and the temperature detection diode 4 is laid out,with the intersection being as the center. A current that flows throughthe MOSFET flows to the source terminal S2 through the MOS1, the drainelectrode 8 and the MOS2 from the source terminal S1. At this time, alarge amount of current flows over the straight line, which is theshortest path, connecting the source terminal S1 and the source terminalS2. When an abnormal current flows, the current reaches a peak over theshortest path, and an amount of heat generation becomes the largest.

As in the First Embodiment, the temperature detection diode 4 isarranged at a position where a current between the source terminal S1and the source terminal S2 reaches the peak, and thus it becomespossible to more accurately detect arise in temperature when theabnormal current flows. In addition, a wiring can be made the shortestby arranging the temperature detection diode 4 under the anode terminalT1, and it becomes possible to extend a region where an MOSFET elementis arranged, i.e., a source aluminum wiring region. Since the sourcealuminum wiring region becomes substantially equal to an active region,the larger the region is, the lower on-resistance the MOSFET has.Because of this, it becomes possible to increase an effective cell areawithout increasing a size.

Here, referring to FIGS. 8A to 8G, a method of manufacturing thesemiconductor device according to the First Embodiment will beexplained. FIGS. 8A to 8G are manufacturing process cross-sectionalviews explaining the method of manufacturing the semiconductor deviceaccording to the First Embodiment. FIGS. 8A to 8G show manufacturingprocesses of the temperature detection diode 4 used for thesemiconductor device 1.

First, as shown in FIG. 8A, after the insulating film 40 such as anoxide film is formed over the semiconductor substrate 5, polysilicon Sis deposited. After that, boron is injected and P-type polysilicon PS isformed (FIG. 8B). After a photoresist (not shown) is formed over theP-type polysilicon PS, the P-type polysilicon PS is etched in apredetermined shape by a known method (FIG. 8C).

After that, an interlayer insulating film 31 a is formed over the P-typepolysilicon PS, and a photoresist PR is formed thereover. By using thephotoresist PR as a mask, injection of arsenic into a part of the P-typepolysilicon PS makes the P-type polysilicon an N-type one. Because ofthis, a structure is formed in which the P-type polysilicon 43 and theN-type polysilicon 44 are alternately aligned (FIG. 8D). Then, afterpeeling of the photoresist PR, an interlayer insulating film 31 b isformed. The interlayer insulating films 31 a and 31 b serve as theinterlayer insulating film (FIG. 8E).

After the interlayer insulating film 31 b is formed, etching isperformed using a photoresist that is not shown, and contact holes CTare formed in a boundary of the P-type polysilicon 43 and the N-typepolysilicon 44 so that the PN junction is cut (FIG. 8F). At this time,further contact holes CT are also simultaneously formed in positionsserving as the anode contact 45 and the cathode contact 46. Then, aftersputtering of a barrier metal is performed, the contact metal 47, theanode contact 45, and the cathode contact 46 are formed in the contactholes CT (FIG. 8G). Note that the same applies to the manufacturingprocesses of the bidirectional Zener diodes 2 and 3 shown in FIG. 7although, in the above-mentioned processes, the formation is made inonly different positions.

As described above, the temperature detection diode 4 can be formed inthe same processes as the manufacturing processes of the bidirectionalZener diodes 2 and 3. Generally, since the bidirectional Zener diodes 2and 3 are mounted for protecting ESD (electro-static discharge), anadditional process is not needed, and it becomes possible to mount thetemperature detection diode 4 without increasing manufacturing cost. Inaddition, in the temperature detection diode 4 of the presentconfiguration, a plurality of diodes is continuously formed by shortingthe NP junction portions by the contact metal 47 so that the PN junctionportions are maintained. Because of this, since the temperaturedetection diode 4 of multistage connection can be achieved by theshortest distance, it becomes possible to form the temperature detectiondiode 4 having a small area.

In FIG. 9, there is shown a circuit diagram of a battery protectioncircuit 100 using the semiconductor device of the First Embodiment. Thebattery protection circuit 100 is provided with the semiconductor device1, a control IC 101, and a current detection resistor 102. A constantcurrent is caused to flow from a constant current source 103 in thecontrol IC 101, to the temperature detection diode 4 in thesemiconductor device 1, and a voltage VF between an anode and a cathodeof the temperature detection diode 4 is monitored. When thesemiconductor device 1 generates heat, the VF changes due to a negativetemperature coefficient of the temperature detection diode 4. Thecontrol IC 101 determines that abnormal heat generation occurs when theVF reaches a predetermined voltage, the control IC 101 switches OFF theMOS1 and the MOS2, and interrupts a current.

In FIGS . 10 and 11 is shown an example in which the battery protectioncircuit 100 shown in FIG. 9 has been mounted on a substrate. FIG. 11 isa diagram when the battery protection circuit 100 shown in FIG. 10 isviewed from a side. The semiconductor device 1, pads 104 and 105, thecontrol IC 101, and the current detection resistor 102 are mounted at asubstrate 106 as shown in FIG. 10. The temperature detection diode 4 isincorporated in the semiconductor device 1, and it is not mounted overthe substrate 106. As described above, the temperature detection diode 4is incorporated in the semiconductor device 1, and thus the number ofparts can be reduced and a mounting area thereof can be reduced.

In addition, the drain electrode 8 is formed on the back surface side ofthe semiconductor device 1, and thus when the semiconductor device 1 ismounted on the substrate 106, the drain electrode 8 is exposed to a topsurface. Therefore, when the temperature detection diode 4 is arrangedover the semiconductor device 1, an insulating sheet needs to bearranged in order to insulate the drain electrode 8. However, in theFirst Embodiment, since the temperature detection diode 4 isincorporated in the semiconductor device 1, the insulating sheet is notneeded, and a mounting height can be reduced as shown in FIG. 11.Therefore, cost reduction and thickness reduction are possible.

Second Embodiment

A semiconductor device according to a Second Embodiment will beexplained with reference to FIG. 12. FIG. 12 is a partially enlargedcross-sectional diagram of a configuration of a temperature detectiondiode 4A used for the semiconductor device according to the SecondEmbodiment. As shown in FIG. 12, the P-type polysilicon 43 has a firstimpurity concentration region 43 a provided on an N-type polysilicon 44side, and a second impurity concentration region 43 b provided on acontact metal 47 side. The second impurity concentration region 43 b hasa higher impurity concentration than the first impurity concentrationregion 43 a.

The impurity concentration of the second impurity concentration region43 b that is in contact with the contact 47 is made higher than thefirst impurity concentration region 43 a as described above, and thussufficient connectivity with the contact 47 can be obtained. Inaddition, since multistage connection of diodes can be realized by theshortest distance in the same way as in the First Embodiment, it becomespossible to form the temperature detection diode 4A having a small area.

In FIGS. 13A to 13I, there are shown manufacturing processcross-sectional views explaining a method of manufacturing thesemiconductor device according to the Second Embodiment. Since FIGS. 13Ato 13C are the same as FIGS. 8A to 8C, explanation thereof is omitted.As shown in FIG. 13D, the interlayer insulating film 31 a is formed overthe P-type polysilicon PS, and over the interlayer insulating film 31 a,the photoresist PR having opening portions is formed in a region servingas the second impurity concentration region 43 b. Boron is injected byusing this photoresist PR as a mask, and the second impurityconcentration region 43 b is formed.

After that, the photoresist PR is peeled (FIG. 13E). Then, as shown inFIG. 13F, another photoresist PR having opening portions is formed in aregion serving as the N-type polysilicon 44 over the interlayerinsulating film 31 a, and injection of arsenic into a part of the P-typepolysilicon PS makes the polysilicon an N-type one. Because of this, astructure, in which the second impurity concentration region 43 b, thefirst impurity concentration region 43 a, and the N-type polysilicon 44are aligned in order, is formed (FIG. 13F). Then, after peeling of thephotoresist PR, the interlayer insulating film 31 b is formed. Theinterlayer insulating films 31 a and 31 b serve as the interlayerinsulating film 31 (FIG. 13G).

After the interlayer insulating film 31 b is formed, etching isperformed using a photoresist that is not shown, and the contact holesCT are formed at a boundary of the second impurity concentration region43 b and the N-type polysilicon 44 (FIG. 13H). At this time, furthercontact holes CT are also simultaneously formed in positions serving inthe leftmost second impurity concentration region 43 b and the rightmostN-type polysilicon 44. Note that the same applies to the manufacturingprocesses of the bidirectional Zener diodes 2 and 3 shown in FIG. 7although, in the above-mentioned processes, the formation is made inonly different positions. Then, after sputtering of the barrier metal,the contact metal 47 is formed in the contact holes CT (FIG. 13I). Inaddition, along with this, the anode contact 45 and the cathode contact46 are also formed.

As described above, the temperature detection diode 4A can be formed inthe same processes as the manufacturing processes of the bidirectionalZener diodes 2 and 3. Because of this, it becomes possible to mount thetemperature detection diode 4A on the semiconductor device 1 withoutincreasing the manufacturing processes.

Third Embodiment

A semiconductor device according to a Third Embodiment will be explainedwith reference to FIG. 14. FIG. 14 is a partially enlargedcross-sectional diagram of a configuration of a temperature detectiondiode 4B used for the semiconductor device according to the ThirdEmbodiment. As shown in FIG. 14, the P-type polysilicon 43 and theN-type polysilicon 44 are alternately formed in a lateral direction overthe insulating film 40. The P-type polysilicon 43 and the N-typepolysilicon 44 are covered with the interlayer insulating film 31.

The contact metal 47 is formed between connection structures of theP-type polysilicon 43 and the N-type polysilicon 44. In the ThirdEmbodiment, unlike the First and Second Embodiments, the contact metal47 has substantially the same height as the P-type polysilicon 43 andthe N-type polysilicon 44, and has a structure covered with theinterlayer insulating film 31.

As described above, the interlayer insulating film 31 is arrangedbetween the contact metal 47 and a layer that forms a wiring layerincluding the source aluminum wiring 11, the source aluminum wiring 21,and the like. Because of this, it becomes possible to form the wiringlayer directly over the temperature detection diode 4B, and to achieve amore efficient layout.

In FIGS. 15A to 15I, there are shown manufacturing processcross-sectional views explaining a method of manufacturing thesemiconductor device according to the Third Embodiment. Since FIGS. 15Ato 15D are the same as FIGS. 8A to 8D, explanation thereof is omitted.After the N-type polysilicon 44 is formed, the photoresist PR is peeled,and a photoresist (not shown) for forming the contact metal 47 isformed. Etching is performed by using this photoresist as a mask, andthe contact holes CT are formed between the connection structures of theP-type polysilicon 43 and the N-type polysilicon 44.

After that, after sputtering of the barrier metal, the contact metal 47is formed in the contact holes CT (FIG. 15F). Then, the interlayerinsulating film 31 b is formed so as to cover the contact metal 47. Theinterlayer insulating films 31 a and 31 b serve as the interlayerinsulating film 31 (FIG. 15G). After the interlayer insulating film 31 bis formed, etching is performed using a photoresist that is not shown,and further contact holes CT are formed in positions serving as theanode contact 45 and the cathode contact 46 (FIG. 15H). Then, aftersputtering of the barrier metal, the anode contact 45 and the cathodecontact 46 are formed in the contact holes CT (FIG. 15I).

Fourth Embodiment

A semiconductor device according to a Fourth Embodiment will beexplained with reference to FIG. 16. FIG. 16 is a circuit diagramshowing a configuration of a semiconductor device 1A according to theFourth Embodiment. In the Fourth Embodiment, a different point from theFirst Embodiment is the point where a protection diode 9 is provided. Inthe Fourth Embodiment, the same symbol is attached to the component asin the First Embodiment, and explanation thereof is omitted.

As shown in FIG. 16, the protection diode 9 is coupled in parallel withthe temperature detection diode 4 and in an opposite direction to thetemperature detection diode 4. A surface layout of the semiconductordevice 1A according to the Fourth Embodiment is shown in FIG. 17. InFIG. 17, a boundary line of the first region 10 and the second region 20is shown by a dashed line. As shown in FIG. 17, the anode terminal T1 isarranged at an intersection of a straight line connecting the sourceterminal S1 and the source terminal S2, and a boundary line of the MOS1and the MOS2. The temperature detection diode 4 is arranged under theanode terminal T1, with the anode terminal T1 being as a center.

In addition, the cathode terminal T2 is arranged at an intersection of astraight line connecting the gate terminal G1 and the gate terminal G2,and the boundary line of the MOS1 and the MOS2. The protection diode 9is arranged under the cathode terminal T2. FIG. 18 is a cross-sectionaldiagram of the semiconductor device 1A taken along a line XVIII-XVIIIshown in FIG. 17. Since the cross-sectional diagram shown in FIG. 18 isthe same as the cross-sectional diagram shown in FIG. 3, explanationthereof is omitted.

FIG. 19 is a cross-sectional diagram of the semiconductor device 1Ataken along a line XIX-XIX shown in FIG. 17. As shown in FIG. 19, theprotection diode 9 is arranged under the cathode terminal T2. Theprotection diode 9 is formed over the semiconductor substrate 5 via theinsulating film 40. A configuration of the protection diode 9 is shownin FIG. 20. FIG. 20 is a diagram when the protection diode 9 is viewedfrom a top surface. As shown in FIG. 20, the protection diode 9 hasN-type polysilicon 91, P-type polysilicon 92, contacts 93, and contacts94. The P-type polysilicon 92 is provided so as to surround an outerperiphery of the N-type polysilicon 91. The N-type polysilicon 91 andthe P-type polysilicon 92 are concentrically arranged, with a formationposition of the cathode terminal T2 being as a center. The contacts 93are provided in the N-type polysilicon 91. The N-type polysilicon 91 iscoupled to the cathode wiring 42 through the contacts 93.

As shown in FIG. 19, the P-type polysilicon 92 is coupled to the anodewiring 41 via the contacts 94. The protection diode 9 can besimultaneously formed by the same processes as the bidirectional Zenerdiodes 2 and 3 and the temperature detection diode 4. Note that thebidirectional Zener diodes 2 and 3 are provided under the gate terminalsG1 and G2, respectively. This configuration is the same as theconfiguration explained in the First Embodiment.

As mentioned above, in the Fourth Embodiment, the protection diode 9 isprovided in parallel with the temperature detection diode 4 in theopposite direction thereto. Therefore, even when a surge such as ESD isapplied to the temperature detection diode 4 in the opposite direction,it becomes possible to absorb the serge by the protection diode 9, andbreakdown of the temperature detection diode 4 can be prevented. Inaddition, in the Fourth Embodiment, the protection diode 9 isconcentrically formed at the lower portion of the cathode terminal T2 ofthe temperature detection diode 4, with the formation position of thecathode terminal T2 being as the center. As described above, theprotection diode 9 can be mounted without an accompanying increase in achip size, by utilization of a region required for mounting thetemperature detection diode 4. Because of this, it becomes possible tosuppress cost increase.

Fifth Embodiment

A semiconductor device according to a Fifth Embodiment will be explainedwith reference to FIG. 21. FIG. 21 is a circuit diagram showing aconfiguration of a semiconductor device 1B according to the FifthEmbodiment. In the Fifth Embodiment, a different point from the FourthEmbodiment is the point where two source terminals are further added. Inthe Fifth Embodiment, the same symbol is attached to the same componentas in the above-mentioned embodiments, and explanation thereof isomitted.

As shown in FIG. 21, a source of the MOS1 is coupled not only to thesource terminal S1 but also to a source terminal S3. In addition, asource of the MOS2 is coupled not only to the source terminal S2 butalso to a source terminal S4. In the Fifth Embodiment, in the same wayas in the Fourth Embodiment, the protection diode 9 is coupled inparallel with the temperature detection diode 4 and in an oppositedirection to the temperature detection diode 4. Note that the protectiondiode 9 may not be provided.

A surface layout of the semiconductor device 1B according to the FourthEmbodiment is shown in FIG. 22. As shown in FIG. 22, in the FifthEmbodiment, there are provided eight terminals of the source terminalsS1, S2, S3, and S4, the gate terminals G1 and G2, the anode terminal T1,and the cathode terminal T2. In FIG. 22, a boundary line of the firstregion 10 and the second region 20 is shown by a dashed line. The sourceterminal S1 and the source terminal S2 are arranged facing each otherwhile sandwiching the boundary line of the first region 10 and thesecond region 20. The source terminal S3 and the source terminal S4 arearranged facing each other while sandwiching the boundary line of thefirst region 10 and the second region 20. The gate terminal G1 and thegate terminal G2 are arranged facing each other while sandwiching theboundary line of the first region 10 and the second region 20.

In the first region 10, the gate terminal G1 is arranged between thesource terminal S1 and the source terminal S3. A distance between thegate terminal G1 and the source terminal S1, and a distance between thegate terminal G1 and the source terminal S3 are substantially equal toeach other. In the second region 20, the gate terminal G2 is arrangedbetween the source terminal S2 and the source terminal S4. A distancebetween the gate terminal G2 and the source terminal S2, and a distancebetween the gate terminal G2 and the source terminal S4 aresubstantially equal to each other. Position deviation when melting ofsolder by heat causes connection can be suppressed by equalizing a pitchof the terminals.

The anode terminal T1 is arranged at an intersection of a straight lineconnecting the source terminal S1 and the source terminal S2, and aboundary line of the MOS1 and the MOS2. The temperature detection diode4 is arranged under the anode terminal T1, with the anode terminal T1being as a center. In addition, the cathode terminal T2 is arranged atan intersection of a straight line connecting the source terminal S3 andthe source terminal S4, and the boundary line of the MOS1 and the MOS2.The protection diode 9 is arranged under the cathode terminal T2.

FIG. 23 is a cross-sectional diagram of the semiconductor device 1Btaken along a line XXIII-XXIII shown in FIG. 22. Since thecross-sectional diagram shown in FIG. 23 is the same as thecross-sectional diagram shown in FIG. 3, explanation thereof will beomitted. FIG. 24 is a cross-sectional diagram of the semiconductordevice 1B taken along a line XXIV-XXIV shown in FIG. 22. In the FifthEmbodiment, no terminal is provided between the gate terminals G1 andG2. The bidirectional Zener diodes 2 and are provided under the gateterminals G1 and G2, respectively. This configuration is the same as theconfiguration explained in the First Embodiment.

FIG. 25 is a cross-sectional diagram of the semiconductor device 1Btaken along a line XXV-XXV shown in FIG. 22. As shown in FIG. 25, theprotection diode 9 is arranged under the cathode terminal T2. Theprotection diode 9 is formed over the semiconductor substrate 5 throughthe insulating film 40. The same configuration as the one shown in FIG.20 can be used as the configuration of the protection diode 9.

In the Fifth Embodiment, a plurality of source terminals is provided atthe MOS1 and the MOS2, respectively, and an effective cell area isincreased. Because of this, it becomes possible to achieve lowon-resistance. In addition, since the temperature detection diode 4 andthe protection diode 9 are incorporated, an effect similar to the abovecan be obtained.

Sixth Embodiment

A semiconductor device according to a Sixth Embodiment will be explainedwith reference to FIG. 26. FIG. 26 is a diagram showing a surface layoutof a semiconductor device 1C according to the Sixth Embodiment. In theSixth Embodiment, a different point from the Fifth Embodiment is thepoint where the temperature detection diode 4 is formed in a distributedmanner in the lower portions of the anode terminal T1 and the cathodeterminal T2. In the Sixth Embodiment, the same symbol is attached to thesame component as in the above-mentioned embodiments, and explanationthereof is omitted. In FIG. 26, a boundary line of the first region 10and the second region 20 is shown by a dashed line.

As shown in FIG. 26, in the Sixth Embodiment, there are provided eightterminals of the source terminals S1, S2, S3, and S4, the gate terminalsG1 and G2, the anode terminal T1, and the cathode terminal T2.Arrangement of these terminals is the same as in the Fifth Embodimentshown in FIG. 22.

The anode terminal T1 is arranged at an intersection of a straight lineconnecting the source terminal S1 and the source terminal S2, and aboundary line of the MOS1 and the MOS2. A temperature detection diode 4a that is a part of the temperature detection diode 4 is arranged underthe anode terminal T1, with the anode terminal T1 being as a center. Inaddition, the cathode terminal T2 is arranged at an intersection of astraight line connecting the source terminal S3 and the source terminalS4, and the boundary line of the MOS1 and the MOS2. A temperaturedetection diode 4 b that is the other portion of the temperaturedetection diode is arranged under the cathode terminal T2, and theprotection diode 9 is not arranged unlike the Fifth Embodiment.

FIG. 27 is a cross-sectional diagram of the semiconductor device 1Ctaken along a line XXVII-XXVII shown in FIG. 26. The cross-sectionaldiagram shown in FIG. 27 is substantially the same as thecross-sectional diagram shown in FIG. 3. While the four-stage diode isarranged under the anode terminal T1 in the First Embodiment, thetemperature detection diode 4 a including two-stage diode is arranged inthe Sixth Embodiment.

FIG. 28 is a cross-sectional diagram of the semiconductor device 1Ctaken along a line XXVIII-XXVIII shown in FIG. 26. In the SixthEmbodiment, no terminal is provided between the gate terminals G1 andG2. The bidirectional Zener diodes 2 and 3 are provided under the gateterminals G1 and G2, respectively. This configuration is the same as theconfiguration explained in the First Embodiment.

FIG. 29 is a cross-sectional diagram of the semiconductor device 1Ctaken along a line XXIX-XXIX shown in FIG. 26. As shown in FIG. 29, thetemperature detection diode 4 b including two-stage diode is arrangedunder the cathode terminal T2. In the Sixth Embodiment, two stages ofdiodes are arranged at lower portions of the anode terminal T1 and thecathode terminal T2, respectively, and these four stages of diodesconstitute the temperature detection diode 4. As described above, thetemperature detection diode 4 is formed in a distributed manner at thelower portion of the anode terminal T1 and the lower portion of thecathode terminal T2, and thus an area of the temperature detection diode4 can be decreased.

Seventh Embodiment

A semiconductor device according to a Seventh Embodiment will beexplained with reference to FIG. 30. FIG. 30 is a diagram showing asurface layout of a semiconductor device 1D according to the SeventhEmbodiment. In FIG. 30, a boundary line of the first region 10 and thesecond region 20 is shown by a dashed line. As shown in FIG. 30, thesource terminal S1 and the gate terminal G2 are arranged facing eachother while sandwiching the boundary line of the first region 10 and thesecond region 20. In addition, the gate terminal G1 and the sourceterminal S2 are arranged facing each other while sandwiching theboundary line of the first region 10 and the second region 20. That is,the source terminal S1 and the source terminal S2 are diagonallyarranged, and the gate terminal G1 and the gate terminal G2 arediagonally arranged.

In the present embodiment, the anode terminal T1 corresponds to thesecond terminal, and the cathode terminal T2 corresponds to the firstterminal. The anode terminal T1 and the cathode terminal T2 are arrangedfacing each other while sandwiching the boundary line of the firstregion 10 and the second region 20. That is, a direction in which theanode terminal T1 and the cathode terminal T2 are aligned is an Xdirection substantially perpendicular to a Y direction in which thesource terminal S1 and the gate terminal G1 are aligned, andsubstantially perpendicular to the Y direction in which the sourceterminal S2 and the gate terminal G2 are aligned.

Over the first region 10, the cathode terminal T2 is arranged betweenthe source terminal S1 and the gate terminal G1. Over the second region20, the anode terminal T1 is arranged between the source terminal S2 andthe gate terminal G2. The temperature detection diode 4 is formed overan intersection of a straight line that passes through the sourceterminal S1 and the source terminal S2, and the boundary line of thefirst region 10 and the second region 20. Note that a configuration ofthe temperature detection diode 4 is the same as the one shown in FIG.5.

In the semiconductor device 1D having the present configuration, acurrent path is formed in a direction of the source terminal S2 via thedrain electrode 8 of the back surface from the source terminal S1. Thetemperature detection diode 4 is laid out over the straight line passingthrough the source terminal S1 and the source terminal S2 , in both ofwhich the largest amount of current flows. Because of this, it becomespossible to more accurately detect rise in temperature when the abnormalcurrent flows.

Eighth Embodiment

A semiconductor device according to an Eighth Embodiment will beexplained with reference to FIG. 31. FIG. 31 is a diagram showing asurface layout of a semiconductor device 1E according to the EighthEmbodiment. In FIG. 31, a boundary line of the first region 10 and thesecond region 20 is shown by a dashed line. As shown in FIG. 31, in theEighth Embodiment, there are provided eight terminals of the sourceterminals S1, S2, S3, and S4, the gate terminals G1 and G2, the anodeterminal T1, and the cathode terminal T2. In the present embodiment, theanode terminal T1 corresponds to the second terminal, and the cathodeterminal T2 corresponds to the first terminal.

In the first region 10, the source terminal S1, the cathode terminal T2,the source terminal S3, and the gate terminal G1 are arranged so as tobe aligned in this order at substantially regular intervals. In thesecond region 20, the source terminal S2, the anode terminal T1, thesource terminal S4, and the gate terminal G2 are arranged so as to bealigned in this order at substantially regular intervals. The sourceterminal S1 and the source terminal S2, the cathode terminal T2 and theanode terminal T1, the source terminal S3 and the source terminal S4,and the gate terminal G1 and the gate terminal G2 are respectivelyarranged facing each other while sandwiching the boundary of the firstregion 10 and the second region 20.

A direction in which the anode terminal T1 and the cathode terminal T2are aligned is an X direction substantially perpendicular to a Ydirection in which the source terminal S1 and the gate terminal G1 arealigned, and substantially perpendicular to the Y direction in which thesource terminal S2 and the gate terminal G2 are aligned. The temperaturedetection diode 4 is arranged under an intersection of a straight linethat passes through the source terminal S1 and the source terminal S4,and a straight line that passes through the source terminal S3 and thesource terminal S2. Note that a configuration of the temperaturedetection diode 4 is the same as the one shown in FIG. 5. Also in thepresent embodiment, the temperature detection diode 4 is laid outbetween the source terminals in which the largest amount of currentflows. Because of this, it becomes possible to more accurately detect arise in temperature when the abnormal current flows.

Hereinbefore, although the invention made by the present inventors havebeen specifically explained on the basis of the embodiments, it isneedless to say that the present invention is not limited to thepreviously mentioned embodiments and can be modified variously withinthe scope not departing from the gist thereof. For example, although theexamples in which aluminum is used as a material of the wirings such asthe source wire and the gate wire have been explained in theabove-mentioned explanation, the material of the wirings is not limitedto aluminum, but it may be an other material such as copper, or alloyincluding one of aluminum and copper.

Although apart or all of the above-described embodiments can also bedescribed as the following appendixes, it is not limited to thefollowing.

(Appendix 1)

A semiconductor device including:

a chip including a first MOSFET formed in a first region, and a secondMOSFET formed in a second region;

a common drain electrode of the first MOSFET and the second MOSFET,which is formed on a back surface of the chip;

a first source terminal and a first gate terminal of the first MOSFET,which are formed on a surface of the chip in the first region;

a second source terminal and a second gate terminal of the secondMOSFET, which are formed at the surface of the chip in the secondregion, and which are arranged so as to be aligned substantiallyparallel to a direction in which the first source terminal and the firstgate terminal are aligned;

a diode that is formed between the first source terminal and the secondsource terminal; and

a first terminal and a second terminal of the diode, which are arrangedso as to be aligned in a first direction substantially parallel to adirection in which the first source terminal and the first gate terminalare aligned.

(Appendix 2)

The semiconductor device according to Appendix 1,

the first source terminal and the second source terminal arranged facingeach other while sandwiching a boundary of the first region and thesecond region;

the first gate terminal and the second gate terminal arranged facingeach other while sandwiching the boundary of the first region and thesecond region;

the first terminal formed between the first source terminal and thesecond source terminal;

the second terminal formed between the first gate terminal and thesecond gate terminal; and

the diode provided at a lower portion of the first terminal.

(Appendix 3)

A semiconductor device including:

a chip including a first MOSFET formed in a first region, and a secondMOSFET formed in a second region;

a common drain electrode of the first MOSFET and the second MOSFET,which is formed on a back surface of the chip;

a first source terminal and a first gate terminal of the first MOSFET,which are formed on a surface of the chip in the first region;

a second source terminal and a second gate terminal of the secondMOSFET, which are formed at the surface of the chip in the secondregion, and which are arranged so as to be aligned substantiallyparallel to a direction in which the first source terminal and the firstgate terminal are aligned;

a diode that is formed between the first source terminal and the secondsource terminal; and

a first terminal and a second terminal of the diode, which are arrangedso as to be aligned substantially perpendicular to a direction in whichthe first source terminal and the first gate terminal are aligned,

in which the first terminal is arranged so as to be sandwiched betweenthe first source terminal and the first gate terminal over the firstregion; and

in which the second terminal is arranged so as to be sandwiched betweenthe second source terminal and the second gate terminal over the secondregion.

(Appendix 4)

The semiconductor device according to Appendix 3, in which the firstsource terminal and the second gate terminal are arranged facing eachother while sandwiching a boundary of the first region and the secondregion,

in which the first gate terminal and the second source terminal arearranged facing each other while sandwiching the boundary of the firstregion and the second region, and

in which the diode is arranged between the first region and the secondregion.

What is claimed is:
 1. A chip comprising: a first MOSFET includingterminals aligned with one another in a first direction; a second MOSFETincluding terminals aligned with one another in the first direction; adiode between the first and the second MOSFETs, the diode includingterminals aligned with one another in either the first direction orsecond direction that is orthogonal to the first direction.
 2. The chipaccording to claim 1, wherein the terminals of the diode include a firstterminal and a second terminal, the first terminal and the secondterminal are aligned in the first direction and are formed between afirst region that includes the first MOSFET and a second region thatincludes the second MOSFET.
 3. The chip according to claim 2, whereinthe diode is formed at a lower portion of the first terminal in across-sectional view.
 4. The chip according to claim 2, wherein thediode is divided into a lower portion of the first terminal and a lowerportion of the second terminal.
 5. The chip according to claim 2,wherein the terminals of the first MOSFET include a first sourceterminal and a first gate terminal, and the terminals of the secondMOSFET include a second source terminal and a second gate terminal,wherein the first source terminal and the second source terminal arearranged facing each other while sandwiching a boundary of the firstregion and the second region, wherein the first gate terminal and thesecond gate terminal are arranged facing each other while sandwichingthe boundary of the first region and the second region, wherein thefirst terminal is formed between the first source terminal and thesecond source terminal, and wherein the second terminal is formedbetween the first gate terminal and the second gate terminal.
 6. Thechip according to claim 5, wherein a distance between the first sourceterminal and the first terminal, and a distance between the secondsource terminal and the first terminal are substantially equal to eachother, and wherein a distance between the first gate terminal and thesecond terminal, and a distance between the second gate terminal and thesecond terminal are substantially equal to each other.
 7. The chipaccording to claim 6, wherein a distance between the first sourceterminal and the first gate terminal, a distance between the secondsource terminal and the second gate terminal, and a distance between thefirst terminal and the second terminal are substantially equal to oneanother.
 8. The chip according to claim 2, further comprising aprotection diode coupled in parallel with the diode and coupled with apolarity that opposes a polarity of the diode.
 9. The chip according toclaim 8, wherein the diode is formed at a lower portion of the firstterminal, and wherein the protection diode is formed at a lower portionof the second terminal.
 10. The chip according to claim 1, wherein theterminals of the diode include a first terminal and a second terminal,wherein the first terminal and the second terminal are aligned in thesecond direction, the diode is formed between a first region thatincludes the first MOSFET and a second region that includes the secondMOSFET, and the first terminal is formed over the first region, and thesecond terminal is formed over the second region.
 11. The chip accordingto claim 10, wherein the terminals of the first MOSFET include a firstsource terminal and a first gate terminal, and the terminals of thesecond MOSFET include a second source terminal and a second gateterminal, wherein the first terminal is arranged so as to be sandwichedbetween the first source terminal and the first gate terminal, andwherein the second terminal is arranged so as to be sandwiched betweenthe second source terminal and the second gate terminal.
 12. The chipaccording to claim 1, wherein the terminals of the first MOSFET includea first source terminal and a first gate terminal, and the terminals ofthe second MOSFET include a second source terminal and a second gateterminal, wherein the first source terminal and the second gate terminalare arranged facing each other while sandwiching a boundary of a firstregion that includes the first MOSFET and a second region that includesthe second MOSFET, wherein the first gate terminal and the second sourceterminal are arranged facing each other while sandwiching the boundaryof the first region and the second region, and wherein the diode isarranged between the first region and the second region.
 13. The chipaccording to claim 1, wherein the terminals of the diode include a firstterminal and a second terminal, wherein the diode is concentricallyconfigured, with the first terminal being as a center.
 14. The chipaccording to claim 13, wherein the diode comprises: a plurality ofconnection structures including a first conductive type semiconductorlayer and a second conductive type semiconductor layer; and a pluralityof contact metals formed between adjacent connection structures, forforming the diode.
 15. The chip according to claim 14, wherein the firstconductive type semiconductor layer comprises: a first impurityconcentration region formed on a second conductive type semiconductorlayer side; and a second impurity concentration region that is formed ona contact side, and that has a higher impurity concentration than thatof the first impurity concentration region.
 16. The chip according toclaim 14, wherein a contact metal from among the plurality of contactmetals has a height substantially equal to that of the first conductivetype semiconductor layer and the second conductive type semiconductorlayer.
 17. The semiconductor device according to claim 1, wherein abidirectional Zener diode is provided between gates and sources of thefirst MOSFET and the second MOSFET, respectively.